View MRF141_152803.PDF datasheet online --- IC-ON-LINE

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SEMICONDUCTOR TECHNICAL DATA
Order this document by MRF141/D
The RF MOSFET Line
RF Powe r Field-E ffec t Transistor
N-Channel Enhancement-Mode MOSFET
Designed for broadband commercial and military applications at frequencies to 175 MHz. The high power, high gain and broadband performance of this device makes possible solid state transmitters for FM broadcast or TV channel frequency bands. * Guaranteed Performance at 30 MHz, 28 V: Output Power -- 150 W Gain -- 18 dB (22 dB Typ) Efficiency -- 40% * Typical Performance at 175 MHz, 50 V: Output Power -- 150 W Gain -- 13 dB * Low Thermal Resistance * Ruggedness Tested at Rated Output Power * Nitride Passivated Die for Enhanced Reliability
S G
MRF141
D
150 W, 28 V, 175 MHz N-CHANNEL BROADBAND RF POWER MOSFET
CASE 211-11, STYLE 2
MAXIMUM RATINGS
Rating Drain-Source Voltage Drain-Gate Voltage Gate-Source Voltage Drain Current -- Continuous Total Device Dissipation @ TC = 25C Derate above 25C Storage Temperature Range Operating Junction Temperature Symbol VDSS VDGO VGS ID PD Tstg TJ Value 65 65 40 16 300 1.71 - 65 to +150 200 Unit Vdc Vdc Vdc Adc Watts W/C C C
THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction to Case Symbol RJC Max 0.6 Unit C/W
NOTE -- CAUTION -- MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be observed.
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ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS (1)
Drain-Source Breakdown Voltage (VGS = 0, ID = 100 mA) Zero Gate Voltage Drain Current (VDS = 28 V, VGS = 0) Gate-Body Leakage Current (VGS = 20 V, VDS = 0) V(BR)DSS IDSS IGSS 65 -- -- -- -- -- -- 5.0 1.0 Vdc mAdc Adc
ON CHARACTERISTICS (1)
Gate Threshold Voltage (VDS = 10 V, ID = 100 mA) Drain-Source On-Voltage (VGS = 10 V, ID = 10 A) Forward Transconductance (VDS = 10 V, ID = 5.0 A) VGS(th) VDS(on) gfs 1.0 0.1 5.0 3.0 0.9 7.0 5.0 1.5 -- Vdc Vdc mhos
DYNAMIC CHARACTERISTICS (1)
Input Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Ciss Coss Crss -- -- -- 350 420 35 -- -- -- pF pF pF
FUNCTIONAL TESTS
Common Source Amplifier Power Gain, f = 30; 30.001 MHz (VDD = 28 V, Pout = 150 W (PEP), IDQ = 250 mA) f = 175 MHz Drain Efficiency (VDD = 28 V, Pout = 150 W (PEP), f = 30; 30.001 MHz, IDQ = 250 mA, ID (Max) = 5.95 A) Intermodulation Distortion (1) (VDD = 28 V, Pout = 150 W (PEP), f = 30 MHz, f2 = 30.001 MHz, IDQ = 250 mA) Load Mismatch (VDD = 28 V, Pout = 150 W (PEP), f1 = 30; 30.001 MHz, IDQ = 250 mA, VSWR 30:1 at all Phase Angles) Gps 16 -- 40 20 10 45 -- -- -- dB %
dB IMD(d3) IMD(d11) No Degradation in Output Power -- -- - 30 - 60 - 28 --
CLASS A PERFORMANCE
Intermodulation Distortion (1) and Power Gain (VDD = 28 V, Pout = 50 W (PEP), f1 = 30 MHz, f2 = 30.001 MHz, IDQ = 4.0 A) GPS IMD(d3) IMD(d9 - 13) -- -- -- 23 - 50 - 75 -- -- -- dB
NOTE: 1. To MIL-STD-1311 Version A, Test Method 2204B, Two Tone, Reference Each Tone.
BIAS + 0 - 12 V -
L1 C11 R4 C5 R1 C2 C3 R2 C12 C6 C4 C7 T2 C8 L2 C9
+ - C10
+ 28 V - RF OUTPUT
D.U.T.
RF INPUT
R3 T1
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C2, C5, C6, C7, C8, C9 -- 0.1 F Ceramic Chip or Monolythic with Short Leads C3 -- Arco 469 C4 -- 820 pF Unencapsulated Mica or Dipped Mica with Short Leads C10 -- 10 F/100 V Electrolytic C11 -- 1 F, 50 V, Tantalum C12 -- 330 pF, Dipped Mica (Short leads)
L1 -- VK200/4B Ferrite Choke or Equivalent, 3.0 H L2 -- Ferrite Bead(s), 2.0 H R1, R2 -- 51 /1.0 W Carbon R3 -- 1.0 /1.0 W Carbon or Parallel Two 2 , 1/2 W Resistors R4 -- 1 k/1/2 W Carbon T1 -- 16:1 Broadband Transformer T2 -- 1:25 Broadband Transformer Board Material -- 0.062 Fiberglass (G10), 1 oz. Copper Clad, 2 Sides, e r = 5
Figure 1. 30 MHz Test Circuit (Class AB) 2
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TYPICAL CHARACTERISTICS
VGS, GATE-SOURCE VOLTAGE (NORMALIZED) 100 I D, DRAIN CURRENT (AMPS) 1.04 1.03 1.02 1.01 1 0.99 0.98 0.97 0.96 0.95 0.94 0.93 0.92 0.91 0.9 - 25
ID = 5 A
4A 2A 1A 0.5 A 0.25 A 0 25 50 TC, CASE TEMPERATURE (C) 75 100
10
TC = 25C 1
1
10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
100
Figure 2. DC Safe Operating Area
Figure 3. Gate-Source Voltage versus Case Temperature
2000 f T, UNITY GAIN FREQUENCY (MHz) VDS = 20 V C, CAPACITANCE (pF) 10 V
200 0 Coss Ciss 200
1000
Crss
0
0
2
4
6 8 10 12 14 ID, DRAIN CURRENT (AMPS)
16
18
20
20 0
5
10
15
20
25
VDS, DRAIN-SOURCE VOLTAGE (VOLTS)
Figure 4. Common Source Unity Gain Frequency versus Drain Current
Figure 5. Capacitance versus Drain-Source Voltage
30 Pout , OUTPUT POWER (WATTS)
300 200 100 00 300 200 100 f = 30 MHz VDD = 28 V IDQ = 250 mA 0 1 2 3 4 5 5 10 15 f = 175 MHz VDD = 28 V IDQ = 250 mA 20 25
25 GPS , POWER GAIN (dB)
20 VDD = 28 V IDQ = 250 mA Pout = 150 W
15
10
5
2
10 f, FREQUENCY (MHz)
100
200
0
Pin, INPUT POWER (WATTS)
Figure 6. Power Gain www..com versus Frequency
Figure 7. Output Power versus Input Power
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TYPICAL CHARACTERISTICS
320 Pout , OUTPUT POWER (WATTS) Pout , OUTPUT POWER (WATTS) 280
f = 30 MHz IDQ = 250 mA
320 280 240 200 160 120 80 40 14 16 18 20 22 24 26 28 0 12 14 16 18 20 22 24 26 28 Pin = 20 W 14 W 8W
f = 175 MHz IDQ = 250 mA
240 200 Pin = 4 W
160 2W 1W 120 80 40 0 12
SUPPLY VOLTAGE (VOLTS)
SUPPLY VOLTAGE (VOLTS)
Figure 8. Output Power versus Supply Voltage
Figure 9. Output Power versus Supply Voltage
IMD, INTERMODULATION DISTORTION (dB)
25 d3 35 45 IDQ = 250 mA 55 VDD = 28, f = 30 MHz, TONE SEPARATION = 1 kHz 25 35 45 55 0 20 40 60 d3 d5
d5 80 100 120 140
IDQ = 500 mA 160 180 200
Pout, OUTPUT POWER (WATTS)
Figure 10. IMD versus Pout (PEP)
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Zo = 10 VDD = 28 V IDQ = 250 mA Pout = 150 W PEP ZOL* = Conjugate of the optimum load impedance ZOL* = into which the device output operates at a ZOL* = given output power, voltage and frequency. 15 7.5 4 2 2 Zin 30 100 150 30 100
f = 175 MHz ZOL* f = 175 MHz
Figure 11. Input and Output Impedances
RFC1 + 28 V + BIAS 0 - 12 V R1 + C4 C5 R3 C1 RF INPUT R2 C6 C7 C8 L1 DUT L3 L2 C9 RF OUTPUT L4 C10 - C11
C2
C3
C1, C2, C8 -- Arco 463 or equivalent C3 -- 25 pF, Unelco C4 -- 0.1 F, Ceramic C5 -- 1.0 F, 15 WV Tantalum C6 -- 25 pF, Unelco J101 C7 -- 25 pF, Unelco J101 C9 -- Arco 262 or equivalent C10 -- 0.05 F, Ceramic C11 -- 15 F, 35 WV Electrolytic
L1 -- 3/4, #18 AWG into Hairpin L2 -- Printed Line, 0.200 x 0.500 L3 -- 7/8, #16 AWG into Hairpin L4 -- 2 Turns, #16 AWG, 5/16 ID RFC1 -- 5.6 H, Molded Choke RFC2 -- VK200-4B R1 -- 150 , 1.0 W Carbon R2 -- 10 k, 1/2 W Carbon R3 -- 120 , 1/2 W Carbon
Figure 12. 175 MHz Test Circuit (Class AB)
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www..com 430 0.970 172
6
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f MHz
440 420 410 400 390 380 370 360 350 340 330 320 310 300 290 280 270 260 250 240 230 220 210 200 190 180 170 160 150 140 130 120 100 110 90 80 70 60 50 40 30
0.970 0.971 0.970 0.970 0.970 0.968 0.966 0.965 0.967 0.967 0.966 0.964 0.966 0.965 0.964 0.963 0.961 0.962 0.961 0.960 0.961 0.958 0.938 0.950 0.950 0.949 0.948 0.946 0.946 0.943 0.941 0.939 0.935 0.934 0.931 0.929 0.927 0.923 0.922 0.919 0.916 |S11|
S11
Table 1. Common Source S-Parameters (VDS = 24 V, ID = 5 A)
-180
-180
-179
-179
-179
-178
-178
-177
171 172 172 173 173 173 174 174 174 174 174 175 175 175 175 176 176 176 176 177 177 178 177 177 178 178 178 179 179 179 179 180 180
|S21|
0.13 0.15 0.17 0.17 0.17 0.18 0.20 0.20 0.21 0.22 0.23 0.22 0.24 0.25 0.26 0.25 0.26 0.27 0.30 0.32 0.36 0.36 0.39 0.43 0.45 0.49 0.52 0.57 0.63 0.67 0.76 0.82 0.91 1.05 1.15 1.28 1.48 1.77 2.14 2.55 3.23 4.23
S21
32 29 30 29 26 31 27 28 28 24 26 21 26 27 27 25 30 30 31 30 28 27 33 31 35 37 37 39 40 42 46 48 51 53 55 60 61 63 68 72 76 83
0.074 0.070 0.076 0.076 0.071 0.063 0.053 0.048 0.062 0.058 0.056 0.056 0.053 0.051 0.047 0.045 0.045 0.044 0.040 0.038 0.036 0.038 0.029 0.043 0.030 0.028 0.026 0.024 0.025 0.024 0.022 0.019 0.017 0.016 0.016 0.015 0.013 0.010 0.010 0.009 0.008 0.011 |S12|
S12
108
76 76 76 78 79 74 74 61 74 78 75 75 75 78 77 78 79 77 76 77 76 77 61 78 74 75 78 73 70 68 67 69 69 66 61 53 48 46 45 39 32
0.933 0.912 0.956 0.982 0.965 0.962 0.931 0.968 0.956 0.946 0.944 0.946 0.947 0.977 0.930 0.940 0.943 0.933 0.918 0.912 0.943 1.033 0.972 0.966 0.915 0.899 0.906 0.891 0.915 0.940 0.926 0.916 0.930 0.913 0.893 0.850 0.864 0.878 0.893 0.914 0.885 0.876 |S22|
S22
-180
-180
-177
167 165 167 169 172 168 168 170 171 171 170 170 171 172 172 172 172 171 174 175 174 174 175 174 176 176 178 178 178 177 179 180 177 178 180 180 179 179 178
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330 0.966 174 www..com
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REV 9
f MHz
f MHz
350 340 320 310 300 290 280 270 260 250 240 230 220 210 200 190 180 170 160 150 140 130 120 100 500 490 480 470 460 450 110 90 80 70 60 50 40 30
0.967 0.967 0.965 0.966 0.965 0.964 0.963 0.961 0.962 0.961 0.960 0.959 0.953 0.949 0.952 0.950 0.950 0.948 0.946 0.945 0.942 0.940 0.938 0.934 0.933 0.930 0.927 0.924 0.920 0.918 0.915 0.914 0.959 0.960 0.964 0.969 0.970 0.970 |S11| |S11|
Table 1. Common Source S-Parameters (VDS = 24 V, ID = 5 A) continued
S11
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Table 2. Common Source S-Parameters (VDS = 28 V, ID = 5 A)
-180
-180
-179
-179
-179
-178
-178
-178
-177
174 174 175 175 175 175 176 176 176 177 177 177 178 177 178 178 178 178 179 179 179 180 180 170 170 170 170 171 171
|S21|
|S21|
0.22 0.24 0.23 0.25 0.26 0.27 0.26 0.27 0.29 0.30 0.33 0.37 0.38 0.41 0.46 0.47 0.52 0.54 0.61 0.67 0.71 0.81 0.88 0.98 1.13 1.23 1.39 1.61 1.92 2.32 2.76 3.51 4.60 0.15 0.15 0.16 0.15 0.15 0.15
S21
S21
22 25 19 23 24 25 23 27 27 27 27 25 26 31 28 33 34 35 37 38 40 44 46 49 51 53 58 60 62 67 71 76 82 23 31 34 30 32 31
0.057 0.054 0.055 0.053 0.052 0.051 0.045 0.042 0.041 0.041 0.042 0.040 0.037 0.019 0.067 0.034 0.029 0.026 0.023 0.021 0.018 0.018 0.018 0.017 0.015 0.012 0.010 0.009 0.010 0.010 0.009 0.008 0.007 0.103 0.107 0.099 0.095 0.090 0.081 |S12| |S12|
S12
S12
79 76 78 81 83 81 79 80 83 86 84 79 76 94 17 64 76 78 77 73 77 82 81 73 63 57 61 62 56 45 34 26 25 68 75 80 77 73 76
0.917 0.929 0.955 0.984 1.012 0.963 0.930 0.929 0.951 0.969 0.972 0.943 1.014 0.954 1.023 0.971 0.959 0.912 0.871 0.910 0.961 0.966 0.959 0.926 0.884 0.875 0.874 0.899 0.887 0.881 0.888 0.879 0.874 0.962 0.947 0.956 0.945 0.982 0.967 |S22| |S22|
S22
S22
-178
-179
-179
-179
-179
-179
-177
-179
-179
-179
-176
170 171 172 171 173 171 172 174 175 176 175 174 174 177 178 177 178 179 179 179 179 179 163 163 165 165 164 167
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Table 2. Common Source S-Parameters (VDS = 28 V, ID = 5 A) continued
f MHz 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 S11 |S11| |S21| 0.21 0.20 0.20 0.19 0.17 0.17 0.16 0.15 0.13 0.15 0.15 0.15 0.16 0.15 0.15 S21 |S12| S12 |S22| S22
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0.967 0.967 0.969 0.970 0.970 0.970 0.972 0.971 0.971 0.971 0.970 0.969 0.964 0.959 0.958 174 174 173 173 173 172 172 172 171 171 171 170 170 170 170 26 26 23 29 25 27 28 27 29 29 32 29 32 29 21 0.060 0.084 0.081 0.072 0.069 0.072 0.078 0.084 0.086 0.087 0.081 0.079 0.081 0.081 0.086 91 89 82 80 80 71 68 70 74 79 72 65 57 54 58 0.978 1.030 0.994 0.963 0.951 0.985 0.970 0.953 0.949 0.962 0.976 0.969 0.972 0.976 0.953 169 167 170 170 172 167 165 165 168 167 164 164 165 165 167
RF POWER MOSFET CONSIDERATIONS
MOSFET CAPACITANCES The physical structure of a MOSFET results in capacitors between the terminals. The metal anode gate structure determines the capacitors from gate-to-drain (Cgd), and gate- to-source (C gs ). The PN junction formed during the fabrication of the MOSFET results in a junction capacitance from drain-to-source (Cds). These capacitances are characterized as input (Ciss), output (Coss) and reverse transfer (Crss) capacitances on data sheets. The relationships between the inter-terminal capacitances and those given on data sheets are shown below. The Ciss can be specified in two ways: 1. Drain shorted to source and positive voltage at the gate. 2. Positive voltage of the drain in respect to source and zero volts at the gate. In the latter case the numbers are lower. However, neither method represents the actual operating conditions in RF applications.
DRAIN Cgd GATE Cds Cgs Ciss = Cgd = Cgs Coss = Cgd = Cds Crss = Cgd
Since this test is performed at a fast sweep speed, heating of the device does not occur. Thus, in normal use, the higher temperatures may degrade these characteristics to some extent. DRAIN CHARACTERISTICS One figure of merit for a FET is its static resistance in the full-on condition. This on-resistance, VDS(on), occurs in the linear region of the output characteristic and is specified under specific test conditions for gate-source voltage and drain current. For MOSFETs, VDS(on) has a positive temperature coefficient and constitutes an important design consideration at high temperatures, because it contributes to the power dissipation within the device. GATE CHARACTERISTICS The gate of the MOSFET is a polysilicon material, and is electrically isolated from the source by a layer of oxide. The input resistance is very high -- on the order of 109 ohms -- resulting in a leakage current of a few nanoamperes. Gate control is achieved by applying a positive voltage slightly in excess of the gate-to-source threshold voltage, VGS(th). Gate Voltage Rating -- Never exceed the gate voltage rating. Exceeding the rated VGS can result in permanent damage to the oxide layer in the gate region. Gate Termination -- The gate of this device is essentially capacitor. Circuits that leave the gate open-circuited or floating should be avoided. These conditions can result in turn- on of the device due to voltage build-up on the input capacitor due to leakage currents or pickup. Gate Protection -- This device does not have an internal monolithic zener diode from gate-to-source. If gate protection is required, an external zener diode is recommended.
SOURCE
LINEARITY AND GAIN CHARACTERISTICS In addition to the typical IMD and power gain data presented, Figure 4 may give the designer www..com additional information on the capabilities of this device. The graph represents the small signal unity current gain frequency at a given drain current level. This is equivalent to fT for bipolar transistors.
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Using a resistor to keep the gate-to-source impedance low also helps damp transients and serves another important function. Voltage transients on the drain can be coupled to the gate through the parasitic gate-drain capacitance. If the gate-to-source impedance and the rate of voltage change on the drain are both high, then the signal coupled to the gate may be large enough to exceed the gate-threshold voltage and turn the device on. HANDLING CONSIDERATIONS When shipping, the devices should be transported only in antistatic bags or conductive foam. Upon removal from the packaging, careful handling procedures should be adhered to. Those handling the devices should wear grounding straps and devices not in the antistatic packaging should be kept in metal tote bins. MOSFETs should be handled by the case and not by the leads, and when testing the device, all leads should make good electrical contact before voltage is applied. As a final note, when placing the FET into the system it is designed for, soldering should be done with a grounded iron. DESIGN CONSIDERATIONS The MRF141 is an RF Power, MOS, N-channel enhancement mode field-effect transistor (FET) designed for HF and VHF power amplifier applications. M/A-COM Application Note AN211A, FETs in Theory and Practice, is suggested reading for those not familiar with the construction and characteristics of FETs.
The major advantages of RF power MOSFETs include high gain, low noise, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can be varied over a wide range with a low power dc control signal. DC BIAS The MRF141 is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied. Drain current flows when a positive voltage is applied to the gate. RF power FETs require forward bias for optimum performance. The value of quiescent drain current (IDQ) is not critical for many applications. The MRF141 was characterized at IDQ = 250 mA, each side, which is the suggested minimum value of IDQ. For special applications such as linear amplification, IDQ may have to be selected to optimize the critical parameters. The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may be just a simple resistive divider network. Some applications may require a more elaborate bias sytem. GAIN CONTROL Power output of the MRF141 may be controlled from its rated value down to zero (negative gain) by varying the dc gate voltage. This feature facilitates the design of manual gain control, AGC/ALC and modulation systems.
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PACKAGE DIMENSIONS
A U M
1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.
Q
M
4
R
B
2
3
D K J H C E
SEATING PLANE
DIM A B C D E H J K M Q R U
INCHES MIN MAX 0.960 0.990 0.465 0.510 0.229 0.275 0.216 0.235 0.084 0.110 0.144 0.178 0.003 0.007 0.435 --- 45 _NOM 0.115 0.130 0.246 0.255 0.720 0.730
MILLIMETERS MIN MAX 24.39 25.14 11.82 12.95 5.82 6.98 5.49 5.96 2.14 2.79 3.66 4.52 0.08 0.17 11.05 --- 45_ NOM 2.93 3.30 6.25 6.47 18.29 18.54
STYLE 2: PIN 1. 2. 3. 4.
SOURCE GATE SOURCE DRAIN
CASE 211-11 ISSUE N
Specifications subject to change without notice. n North America: Tel. (800) 366-2266, Fax (800) 618-8883 n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298 www..com n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020
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